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| CALIFORNIA MICRO DEVICES PACS1284-06 P/AcitveTM IEEE 1284 ECP/EPP Termination Network Features * Single chip IEEE 1284 parallel port termination * 28 pin QSOP package, smallest physical solution * 17 terminating lines in a single package * In system ESD protection to 8KV, HBM * In system ESD protection to 4KV per IEC1000-4-2 * Protects downstream devices to 30V Applications * ECP/EPP Parallel Port termination * PC Peripherals * Notebook and Desktop computers * Engineering Workstations and Servers Product Description California Micro Devices' PACS1284-06 Parallel Port Termination Network provides a complete integrated solution for the entire IEEE 1284 interface in a single QSOP package. Advanced, enhanced high-speed parallel ports, conforming to the IEEE 1284 standard, are used to provide communications with external devices such as tape back-up drives, ZIP drives, printers, parallel port SCSI adapters, external LAN adapters, scanners, video capture, and other PC peripherals. These advanced ports support bi-directional transfers to 2MB/sec. To effectively support these higher transfer data rates, the IEEE 1284 standard recommends a combined termination, pull-up filter network between the driver/receiver and the cable at both ends of the parallel port interface. In addition, government EMC compatibility requirements impose strict filtering on the parallel port. California Micro Devices' PACS1284-06 Parallel Port Termination Network addresses all of these requirements by providing a seventeen line, IEEE 1284 compliant network in a thin film integrated circuit. The device provides a complete parallel port termination solution for space critical applications by integrating a total of 43 discrete components. In addition, all I/O pins are ESD protected for contact discharges up to 4KV per the Human Body Model. However, the output pins of the device which have the highest probability of exposure to ESD pulses are protected to 8KV, HBM, thereby providing the necessary robustness for the port's application environment. California Micro Devices' P/Active technology provides high reliability and low cost through manufacturing efficiency. The resistors and capacitors are fabricated using proprietary state-of-the-art thin film technology. California Micro Devices' solution is silicon-based and has the same reliability characteristics as today's integrated circuits. SCHEMATIC CONFIGURATION S TA N D A R D PA R T O R D E R I N G I N F O R M AT I O N Package Pins 28 Style QSOP Tubes PACS1284-06Q/T Ordering Part Number Tape & Reel PACS1284-06Q/R Part Marking PACS1284-06Q C1380800 (c) 2000 California Micro Devices Corp. All rights reserved. 8/25/2000 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES PACS1284-06 S TA N D A R D S P E C I F I C AT I O N S Ab s o l u t e To l e r a n c e ( R) Ab s o l u t e To l e r a n c e ( C) Op e r a t i n g Te mp e r a t u r e Ra n g e V CC Powe r Ra t i n g / Re s i s t o r M a x i mu m L e a k a g e C u r r e n t ( @V CC M a x ) Si g n a l Cl a mp Vo l t a g e : Po s i t i ve Cl a mp N e g a t i ve C l a m p St o r a g e Te mp e r a t u r e Pa ck a g e Powe r Ra n g e 10% 20% 0C to 70C 6V Max 100mW 1A @ 25C >6V <-6V -65C to 150C 1. 00W Max S TA N D A R D VA L U E S R1 () ) 1K R1 () ) 39 R1 () ) 5.1K R1 () ) 150pF E S D S P E C I F I C AT I O N S MIN ESD Protection* Peak Discharg Voltage at nay I/O, Human Body Model, Method 3015 (Note 1) InSystem Protection, HBM (Note 2) InSystem Protection, IEC 1000-4-2, Level 2 (Note 2,3) Channel Clamp Voltage @ 8KV ESD Pulses, HBM (Note 1,2) * Guaranteed by design Note 1: Human Body Model per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5 K, pin 20 @ 5V and pin 22 @ ground. Note 2: Pin 22 grounded, pin 20 to VCC, all other pins are open. ESD contact discharge between ground and pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23 through 28, one at a time. Note 3: Standard IEC 1000-4-2 with CDischarge = 150pF, RDischarge = 330, pin 20 @ 5V and pin 22 @ ground. MAX 4KV 8KV 4KV 30KV -4KV -8KV -4KV -30KV (c)2000 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 8/25/2000 CALIFORNIA MICRO DEVICES PACS1284-06 Application Information The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status lines (8 in total) only require a pull-up resistor and a filter capacitor. The Data lines and Strobe also require a series termination resistor in addition to the pull resistors and filter capacitors. See Table 1 and Schematic Diagram. SIGNAL NAME Data1 - Data8 Strobe Init AutoFeedXT Selectin Ack Busy Paper Empty Select Fault SERIES TERMINATION Yes Yes Not Required Not Required Not Required Not Required Not Required Not Required Not Required Not Required IEEE 1284 defines three interface connectors: - 1284 A is a 25-pin DB series connector which is the defacto PC standard for the host connection. - 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device. - 1284 C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral. Figure 1 shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACS1284-06, illustrating how the pin configuration of the PACS1284-06 allows for easy interconnects between the two. The dotted I/ O signals of the PACS1284-06 will typically be connected to a Super I/O chip on the motherboard. Figure 2 shows a possible hook-up between the 1284-B connector on a peripheral and the PACS1284-06. Figure 3 shows a possible hook-up between the 1284-C connector and the PACS1284-06. 1284-A Connector Host 14 25 19 1 1284-B Connector Peripheral 36 19 13 1 18 1 2 20 1284-C Connector Host/Peripheral 36 18 SUPER 1284 1 SUPER 1284 SUPER 1284 = FLOW THROUGH SIGNALS 1 = GND = VCC 1 Figure 1 Figure 2 Figure 3 Sample Hook-ups of IEEE 1284 Connectors and PACS1284-06. (connector and PACS1284-06 not drawn to scale) (c) 2000 California Micro Devices Corp. All rights reserved. 8/25/2000 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CALIFORNIA MICRO DEVICES PACS1284-06 Table 2 defines the signals for the three connectors. PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1284-A 25-PINDSUB STROBE Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ACK BUSY PError Select AUTOFD FAULT INIT Selectin Ground Ground Ground Ground Ground Ground Ground Ground 1284-B 36-PIN CHAMP STROBE Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ACK BUSY PError Select AUTOFD Not Defined Logic Ground Chassis Ground Peripheral Logic Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground INIT FAULT Not Defined Not Defined Not Defined Selectin 1284-C 36-PIN HIGH DENSITY BUSY Select ACK FAULT PError Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 INIT STROBE Selectin AUTOFD Host Logic High Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Not Required Table 2. IEEE 1284 Connector Pinouts. When connecting a 1284-A host to a 1284-B peripheral the "Peripheral Logic High" signal is not used. Similarly, when a 1284-A host is connected to a 1284-C peripheral the "Peripheral Logic High" and "Host Logic High" are not used. These two signals are optionally used to detect a "Power Off" or "Cable Disconnect" state for host and peripheral respectively. (c)2000 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 8/25/2000 CALIFORNIA MICRO DEVICES PACS1284-06 Figure 4 shows typical Insertion Loss graphs for the PACS1284-06 for Data and Strobe signals. The curves are dependent on the physical location of the filter elements with respect to the ground and VCC terminals of the device. These graphs are measured in a 50 Ohm environment. The signal is introduced at the series resistor input and the output is measured at the corresponding filter capacitor. The graphs labeled A,B, and C are measured between 14 (input) and 16 (output), pin 3 (input) and 26 (output), and pin 6 (input) and 23 (output), respectively. The A graph depicts "worst case" filter performance, while C represents a "best case" situation. Graphs of all other filter elements will fall in between these two. S12 in dB 0 -10 A -20 B -30 C -40 -50 300 450 600 750 900 1050 1200 (FREQUENCY, MHz) Figure 4. Typical Filter Insertion Loss for PACS1284-06 (S12 in dB, TA = 25O C) Filter insertion loss is measured using Hewlett Packard HP 8753C Analyzer (c) 2000 California Micro Devices Corp. All rights reserved. 8/25/2000 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5 |
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